module flip_flop (
    input wire  sys_clk      ,
    input wire  sys_ret_n    ,
    input wire  key_in       ,

    output reg  led_out   
);
    
always @(posedge sys_clk )begin//or negedge sys_ret_n)  //异步复位同步释放
    if(sys_ret_n == 1'b0)
        led_out <= 1'b0;
    else
        led_out <= key_in;
end

endmodule